This disclosure relates in general to the field of automatic test equipment (ATE) for DC-DC converters and, more particularly, to a current limit test implemented by such ATE for a high power switching regulator.
ATE tests a device (e.g., an integrated circuit (IC)) by automatically taking measurements and evaluating the results thereof. In some cases, the ATE performs tests using IC pins in a design for test (DFT) structure.
One example of an IC that can be tested with ATE is a high-power DC-DC converter. In some implementations, the high power DC-DC converter includes two transistors as switches: a high-side transistor and a low-side transistor. To address efficiency concerns, a power n-channel metal-oxide-semiconductor (MOS) field-effect transistor (FET) can be used as the high-side switching transistor. Current limit protection can be implemented by sensing a peak current of the high-side power MOSFET.
Variation inherent in the manufacturing processes of semiconductor devices introduces non-idealities into those devices. Similarly, such variation can lead to a mismatch between the elements of a device. Accordingly, to address these non-idealities, some characteristics, such as a current limit threshold, need to be trimmed on a chip-by-chip basis.
FIG. 1 generally shows a conventional current limit process implemented by ATE on a DFT structure. The IC 110 illustrated in FIG. 1 includes a high-side (HS) power NMOS transistor 112 and a low-side (LS) MOS transistor (not pictured). The LS MOS is, for example, an N-type transistor having a drain connected to a source of the HS power NMOS 112. The IC 110 also includes a current sense amplifier 114, a variable current source 116, and a current limit comparator 118.
The current sense amplifier 114 samples a voltage difference between a drain and a source of the HS power NMOS transistor 112. The current sense amplifier 114 outputs a voltage signal (not pictured) or a current signal (e.g., Isense) proportional to the drain current of the HS power NMOS transistor 112. The current limit comparator 118 can receive the sensed current signal Isense and compare that signal with a reference current Iref provided by the variable current source 116. The current limit comparator 118 transits from, e.g., a low signal to a high signal, when the sensed current signal Isense becomes larger than the reference current Iref.
In the current limit process illustrated in FIG. 1, the ATE provides a current source 120, a voltage meter 122, and voltage sources V1 and V2. The current source 120 sources a target current ICL at a pin connected to a source of the HS power NMOS transistor 112 (e.g., at a SW pin of the IC). Then, the ATE sends trim codes to the IC 110 to instruct the variable current source 116 to sweep the reference current Iref. The voltage meter 122 measures when the voltage output by the current limit comparator 118 transits. Thus, the ATE is able to determine the trim code that causes the output of the current limit comparator 118 to transit.
In a large output current application, the current ICL can be desired to be much larger than the current capacity of the ATE. For example, the current ICL can be desired to reach 15 amperes, although some ATE can only provide a maximum current source of 2 amperes. In such a scenario, if ICL is greater than 2 amperes, the ATE cannot source the desired current ICL. Hence, another method is needed to emulate this process.
Some products use a sense SW pin or a sense PVIN pin to test a resistance between a drain and a source of a transistor when the transistor is on. However, those products need an extra PVIN pin or an extra SW pin. Such extra pins are not necessarily available in an actual application.
Another conventional method uses a test structure as shown in FIG. 2. In this method, a small sense FET 212 is used to emulate the resistance of the HS power NMOS transistor 112, rather than using the HS power NMOS transistor 112 itself. Then, the ATE can directly source a current IT from a pin connected to a source of the small sense FET 212 (e.g., from the SW pin) to determine an optimal trimming code. However, this method introduces an error due to a mismatch between the HS power NMOS transistor 112 and the small sense FET 212. In addition, this method needs a more complex layout and extra area for the small sense FET 212 and its driver circuit.